Application Specific Integrated Circuits (ASICS) in conjunction with Electronic Circuit Boards (ECBs) are prevalent in today's electronics as they are becoming more functional and easier and cheaper to manufacture. As a result, the need to test an ASIC or ECB after manufacture for the purposes of quality assurance has arisen. Various tests involving forced logical values at electronic circuit inputs can be performed on the ASIC or ECB to verify that the design has been implemented correctly. Typically, because the design is known beforehand, a forced logical value at each input point will yield an expected logical value at each output which can be monitored to verify the expected results with respect to every possible combination of input values.
In the past, a technician would typically connect each input of an electronic circuit to be tested to a logic-value generator and each output to a logic-value reader. Then, the technician could force the inputs to a specific pattern of logical values (e.g., ones and zeroes) to determine if the output points behaved as expected. This, of course, becomes very time and labor intensive for larger ASICs and ECBs. As such, tools, such as an Automatic Test Pattern Generator (ATPG), were developed to alleviate the time and labor involved. With an ATPG, the technician only needs to configure the ATPG once with the correct parameters for the electronic circuit to be tested and then place it in the ATPG. The ATPG is then able to test the electronic circuit using every possible combination of inputs to verify expected outputs. This test, which is sometimes called a scan vector test or simply, scan vectors, may be easily repeated for other similar electronic circuits.
Scan vectors work very well for electronic circuits that only have logical circuitry. However, some electronic circuits also have memory blocks that are not as predictable as logical circuits. More specifically, memory blocks, such as Random Access Memory (RAM), are very difficult to test when part of an electronic circuit because predicting the value at an output of a RAM block based on the input requires knowledge of the values currently stored in the cells of the RAM block. Thus, the technician would again need to individually test each and every input and output without the benefit of automation using an ATPG.
FIG. 1 is a schematic drawing of a conventional electronic circuit having a RAM block 100 that includes associated input logic 110 and output logic 120. The associated input logic 110 and output logic 120 is typically included in a package operable to interface with a larger electronic system (not shown). The input logic 110 and the output logic 120 are typically designed to provide the appropriate logical interface with the RAM block 100 since the RAM block 100 is typically a standard, “off-the-shelf” item. As such, for the larger electronic system to interface with the RAM block 100, input logic 110 and output logic 120 are designed to provide signal paths to and from the RAM block 100. Furthermore, in FIG. 1 and throughout this disclosure, memory blocks, such as RAM block 100 include many inputs and many outputs, but only one input path 101 and one output path 102 is shown for clarity.
As discussed above, predicting the logic value at the output 102 of the RAM block 100 based on the logic value at the input 101 is not easily accomplished in a testing environment. This also makes it difficult to observe the inputs 101 of the RAM block 100. In FIG. 1, two test flip-flops, a launch flip-flop 111 and a capture flip-flop 121, are used to interface the input logic 110 and the output logic 120, respectively. In a typical testing situation, known logic values forced at the launch flip-flop 111 will necessarily cause predictable logic values at the capture flip-flop 121. However, because the RAM block 100 is not predictable, there is no way to verify the design of the input logic 110 and output logic 120 because the logic value at the capture flip-flop 121 cannot be predicted based upon the logic value forced at the launch flip-flop 111. Thus, in an electronic circuit such as in FIG. 1, conventional means for verifying the logical circuitry comprising the input logic 110 and the output logic 120 cannot be used. As a result, the input logic 110 and the output logic 120 remain untested and unverified.
FIG. 2 is a schematic diagram of a conventional electronic circuit having a solution of the past that implements a bypass circuit in conjunction with a RAM block 200. In this solution, a bypass multiplexor 205 is used to select between the actual output signal at the output 202 of the RAM block 200 or a bypass signal on a bypass signal line 230 connected directly to the input of the RAM block 200. A scan mode bit 206 sets the bypass multiplexor 205 to select one signal over the other. By setting the scan mode bit 206 at the multiplexor 205 to a high logic value, a signal on the bypass signal line 230 is allowed to pass through the bypass multiplexor 205 and a signal from the output 202 of the RAM block 200 is ignored. In this manner, a technician can predict exactly how the entire logical path between the input logic 210 and the output logic 220 will behave. Thus, a conventional scan vector test used in an ATPG will be able to verify the input logic 210 and output logic 220 when the scan mode bit 206 is set to a high logic value.
On the other hand, when not in scan mode (i.e., scan mode bit 206 is set to a low logic value), any signal that reaches the input 201 of the RAM block 200 propagates normally through the RAM block 200 and a logic value is generated at the output 202 of the RAM block 200 accordingly. The output logic value passes through the bypass multiplexor 205 to the output logic 220 because the Scan Mode bit 206 is set to a low logic value at the bypass multiplexor 205. At the same time, any signal that propagates on the bypass signal line 230 will terminate at the bypass multiplexor 205 because the scan mode bit 206 is set to a low logic value. As a result, the entire electronic circuit behaves as though no bypass circuit were present.
Some problems, however, present themselves with this solution. One such problem involves timing exceptions that arise when the logical path is tested using a bypass circuit. Typically, during a test using an ATPG to generate scan vectors, it is desirable to do so “at-speed.” That is, it is more beneficial to test the electronic circuit at the speed at which it normally operates which implies proper timing with respect to the number of clock cycles and the period of those clock cycles. As such, an electronic circuit having a RAM block 200 between input logic 210 and output logic 220 will take two clock cycles for an operation to complete. During a first clock cycle, a logic value is input to the RAM block 200 and during a second clock cycle, the RAM block 200 generates a logical output value. As a result, the typical operation of the circuit in FIG. 2 requires two clock cycles for signals to propagate from the launch flip-flop 211 to the capture flip-flop 221.
In scan mode (i.e., scan mode bit 206 is set to a high logic value), however, the logic value propagates from the input logic 210 through the bypass signal line 230 to the output logic 220 on a single clock cycle. Thus, a timing problem arises when testing the logical circuits 210 and 220. The timing problem is caused by the fact that the data must propagate through both input logic 210 and output logic 220 in one clock cycle during scan model, while in non-scan mode (scan mode bit 206 is set to a low logic value) the data has almost 2 clock cycles to propagate through the same logic (input logic 210 and output logic 220). Thus, the test results do not accurately reflect the actual performance of the electronic circuit. This problem makes it difficult or impossible to test this particular path “at-speed” with respect to the larger electronic system in which the electronic circuit is part (i.e., the ASIC).
FIG. 3 is a schematic diagram of a conventional electronic circuit that includes a bypass flip-flop 340, between the input logic 310 and the multiplexor 305, which solves the timing issues discussed above with respect to FIG. 2. In this solution, like the one discussed above in FIG. 2, a bypass multiplexor 305 is used to select between the actual output signal at the output 302 of the RAM block 300 or a bypass signal on a bypass signal line 330 connected directly to the input of the RAM block 300. A scan mode bit 306 sets the bypass multiplexor 305 to select one signal over the other. Again, by setting the scan mode bit 306 to a high logic value, a signal from the bypass flip flop 340 is allowed to pass through the bypass mutiplexor 305 and any signal from the output 302 of the RAM block 300 is rejected. In this manner, a technician can predict exactly how the entire logical path between the input logic 310 and the output logic 320 will behave. Thus, a conventional scan vector test using an ATPG will be able to verify the input and output logic 310 and 320 when the scan mode bit 306 is set to a high logic value.
The bypass signal line flip-flop 340 provides a capture device that passes the value of the signal on the input 301 of the RAM block 300 to the multiplexor 305 on a subsequent clock signal. As a result, in scan mode (i.e., when the scan mode bit 306 is set to a high logic value), the signal propagating though the bypass signal line 330 and the bypass signal line flip-flop 340 behave more like the RAM block 300 because two clock cycles are used to fully propagate signals from the launch flip-flop 311 to the capture flip-flop 321.
This solution allows the electronic circuit to be tested “at-speed” with respect to the rest of the electronic system (i.e., the ASIC); however, other problems are still present. In some electronic circuits, the critical path is very important, and any additional circuitry that is inserted into the electronic circuit may affect the critical path, i.e., add time to the propagation of signals through the electronic circuit. As such, the bypass multiplexor 205 and 305 of either FIG. 2 or FIG. 3 may add to the critical path. Typically, an added multiplexor may cause a timing addition of 100 picoseconds or more which is unacceptable for high-performance electronic circuits.
FIG. 4 is a schematic diagram of yet another conventional circuit for testing logic in an electronic circuit that includes a RAM block 400 or other similar memory block. Instead of a bypass multiplexor of the previous solutions in FIG. 2 and FIG. 3, the electronic circuit of FIG. 4 utilizes registered tri-state circuitry. Some RAM blocks 400 or other memory blocks are available with outputs 402 that are tri-state capable.
Devices that are tri-state enabled use an enable bit, such as scan mode bit 406, to set each respective output 402 to be enabled. Thus, when tri-state outputs 402 are enabled (i.e., the scan mode bit 406 is set to a low logic value), the outputs 402 of the RAM block 400 function normally. During a scan test, however, the scan mode bit 406 may be set to a high logic value and the outputs 402 of the RAM block 400 are then disabled. At the same time, a bypass signal line 430 which is connected directly to the inputs 401 of the RAM block 400 are coupled to a bypass tri-state driver 405, such that the signal on the bypass signal line 430 is allowed to pass when the scan mode bit 406 is set to a high logic value. In this manner, a technician can again predict exactly how the entire logical path between the input logic 410 and the output logic 420 will behave because the input signal bypasses the RAM block 400 through the bypass signal line 430 during a scan test. Therefore, a conventional scan vector test in an ATPG will be able to verify the input logic 410 and output logic 420.
The conventional solution of FIG. 4 also suffers from similar problems that the conventional solutions of FIG. 2 and FIG. 3. For example, the solution still requires additional circuitry for the bypass signal line 430 in addition to requiring that the RAM block 400 have tri-state outputs. This requirement then leads to more complicated interfaces with the ATPG which may not be configured to handle tri-state circuitry. Furthermore, devices having tri-state driver outputs maybe more expensive than devices that have normal outputs in terms of size and performance. Additionally, as was the case before, the critical path timing is still impacted because tri-state driver 405 and the bypass flip-flop 440 add loading which will lead to additional propagation time.